>>Advanced Encryption Standard G2 IP Core datasheet
Security IP Cores and Services
Algotronix' current product portfolio is based around the NIST qualified 'Generation 2' G2 implementation of the AES algorithm which offers highly competitive performance while remaining the most flexible and easy to use AES core available.
Using a high quality IP core in your design will normally be less expensive and time-consuming than implementing the function yourself: it will also often result in higher performance. Moreover the IP core provides a 'living' design component which will continue to be maintained after your own development project is concluded.
Algotronix can also provide a design service to extend or tailor the core to meet the specific requirements of your application.
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AES G2 IP Core Products List |
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| AES IP core implementing NIST publications FIPS197, SP800-38A and AESAVS | |
| Platinum Edition | Complete core set up for portability across FPGA vendors or use in an ASIC |
| Xilinx Edition | Core configured to support Xilinx FPGA families |
| Altera Edition | Core configured to support Altera FPGA families |
| Actel Edition | Core configured to support Actel FPGA families |
| Resources | |
| AES G2 Throughput and Area Calculator (Excel Spreadsheet) | Available by e-mail request |
| AES G2 Reference Designs | |
AES Processor Interface |
Provides a memory mapped register interface to the G2 core |
AES Getting Started |
Demonstrates the G2 core on FPGA vendor evaluation boards |
G3 Advanced Encryption Standard Core
The G3 AES core family is the third generation of Algotronix' AES technology. The G3 core is designed without compromise to be the most efficient and flexible implementation of AES available.
A significant enhancement in the G3 product line is that the widths of internal data paths can be selected by the user using compilation parameters to allow an optimal tradeoff between area and performance. The G3 core supports a full range of AES implementations from ultra small cores targetting a CPLD to multi-gigabit parallelised cores running on advanced FPGAs.
The initial release of the G3 product family is targetted at Xilinx FPGAs. Future releases will extend support to other FPGA vendors and ASICs.
The G3 core can be supplied as synthesisable VHDL source code or as a compiled netlist.
AES G3 Core Product Family |
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| Next Generation AES IP Core Family with significantly improved performance and flexibility | |
| AES | G3 AES core configured to target Xilinx FPGAs |
| AES-Keywrap | Implementation of the AES Keywrap algorithm for securely transferring cryptographic keys |
| AES-LRW | Implementation of the LRW algorithm for encrypting data in place on disk or tape storage |
| AES-GCM | Implementation of the GCM algorithm for protecting high speed data channels |
| G3 Product Brochure | Brochure download (PDF 820kB) |
To obtain a price quotation or arrange an evaluation of the Algotronix' AES Core please e-mail sales@shwltech.com .