●Veritak Verilog-HDL Simulator
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The EYES tool uses a patented technique that involves taking a large number of small layout samples from the IC layout and extracting property measurements ( critical areas etc.) from these samples. These measurements are then used to estimate the properties of the IC layout as a whole. Typically, 4096 samples are used, which for most of todays chips represent less than 1% of the chip area.
The PEYE-CAA tool provides the ability to generate and display detailed critical areas of an IC design layout. It also has the ability to find the critical area between defined nodes , and so can be used to find the probability of different faults. Typically it would be used by a designer to review the layout of cells and small portions of designs. Ideally this would be done interactively within a layout editor. At present the tools can be interfaced to the, reasonably priced, slam editor from Stabie-Soft (an older interface to the Cadence layout editor is also available). Alternatively a GDSII file of the cell or design can be used as input, with output directed to a postscript file which can be displayed or printed.
The PEYE tool is a layout modification/analysis tool for the automation of yield and reliability enhancement of IC layout and to search out layout that is not optimal. The peye tool combines a sophisticated polygon library with Perl (Practical Extraction and Reporting Language). The tool permits complex layout modification operations to be defined using the powerful language features of Perl. PEYE has been used to add contacts/vias to designs and has also been used as a wire spreader .
